EP80579 Datasheet, PDF (291/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• The memory controller does not support any atomic operations. Other units
upstream support atomic operations.
• All memory controller operations are aligned on a 64B boundary
• The memory controller interleaves the memory across banks on a 64B boundary
— Any transaction that crosses a 64B alignment boundary or is larger than 64B
must be split by the upstream agent.
• Supports external DIMMs or SO-DIMMs.
11.3
Configurations
Table 11-1 shows the various DDR2 device densities and widths supported by the
memory controller.
Table 11-1. Supported DDR2 Device Densities and Width
Density (Mb)
256
512
1024
2048
4096
DDR2x8
Supported
Supported
Supported
Supported
Not Supported
Table 11-2 shows the various capacity configurations supported in 64b mode. The first
column shows the total DRAM capacity on the channel. The rest of the columns indicate
the DRAM devices features, densities and the number of devices required to achieve
the given capacity. A single sided DIMM is indicated by no parts populated on side B.
Double sided DIMM has parts populated on both sides.
For each configuration, an additional DRAM part per side is required to support ECC
bits. A x8 part provides all the bits required for ECC. Note that memory system can be
built without ECC enabled.
In the 64b configuration, the minimum capacity supported is 256 MB and the maximum
capacity supported is 4 GB.
Table 11-2. Supported DRAM Capacity for 64b Mode
Total DRAM
Capacity
256 MB
512 MB
1 GB
2 GB
4 GB
DRAM
Density
256 Mb
256 Mb
512 Mb
512 Mb
1 Gb
1 Gb
2 Gb
2 Gb
DRAM
Part
Width
x8
x8
x8
x8
x8
x8
x8
x8
Total # of
parts on
side A
(w/o
ECC)
Total # of
parts on
side B
(w/o
ECC)
8
0
8
8
8
0
8
8
8
0
8
8
8
0
8
8
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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