EP80579 Datasheet, PDF (537/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-155.Offset 1Eh: SECSTS - Secondary Status Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 1Eh
Offset End: 1Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 1Eh
Offset End: 1Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
14
13
12
11
10 : 09
08
07
06
05
04 : 00
Bit Acronym
Bit Description
Sticky
2RSE
2RMAS
2RTAS
STAS
DEVT
DPD
FB2B
Reserved
CAP66
Reserved
Received System Error: Indicates whether or not an
ERR_FATAL or ERR_NONFATAL message was received via
PCI Express*.
0 = Error message not received by this device.
1 = This device received fatal or non-fatal error message
via PCI Express*.
Software clears this bit by writing a ‘1’ to the bit location.
This bit is not set for virtual messages.
Received Master Abort Status: Indicates whether or not
this PCI Express* device received a completion with
Unsupported Request Completion status.
0 = No Master Abort received. Software clears this bit by
writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device receives a
completion with Unsupported Request Completion
Status.
Received Target Abort Status: Indicates whether or not
this PCI Express* device received a completion with
Completer Abort Completion Status.
0 = No Target Abort received. Software clears this bit by
writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device receives a
completion with Completer Abort Completion Status.
Signaled Target Abort Status: Indicates whether or not
this PCI Express* device completed a request using
Completer Abort Completion Status.
0 = No Target Abort signaled. Software clears this bit by
writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device completes a
request using Completer Abort Completion Status.
DEVSEL# Timing: Not Applicable
Master Data Parity Error Detected: Parity is supported
on the secondary side of this device.
0 = No Master Parity Error detected. Software clears this
bit by writing a ‘1’ to the bit location.
1 = Set when this PCI Express* device receives a
completion marked poisoned, or when this device
poisons a write Request. This bit can only be set if the
Parity Error Enable bit is set.
Fast Back-to-Back: Hardwired to 0. Not Applicable to PCI
Express*.
Reserved
Capability 66 MHz: Not Applicableto PCI Express*.
Hardwired to 0.
Reserved
Bit Reset
Value
0b
0b
0b
0b
00b
0b
0b
0b
0b
00h
Bit Access
RWC
RWC
RWC
RWC
RO
RWC
RO
RO
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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