EP80579 Datasheet, PDF (1567/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 38-11. Offset 0x00000060h: SSP_DRIVE - SSP Drive Register
Description: Drive Control of SSP outputs.
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:3:0
Offset Start: 00000060h
Offset End: 00000063h
Size: 32 bit
Default: 02000200h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 :12
11 :8
07 :00
RSVD
Reserved
mdio_pchan_5x Drive strength for P-channel at 5x ratio
mdio_pchan_1x Drive strength for P-channel at 1x ratio
Sticky
Bit Reset
Value
0h
02h
0h
Bit Access
RV
RW
RW
38.4.1.10 Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM
Port 3
Table 38-12. Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM ports 3
Description: Drive Control of TDM port 3outputs
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:3:0
Offset Start: 00000064h
Offset End: 00000067h
Size: 32 bit
Default: 02000200h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 :28
27 :24
23 :16
15 :12
11 :8
07 :00
RSVD
Reserved
mdio_nchan_5x Drive strength for N-channel at 5x ratio
mdio_nchan_1x Drive strength for N-channel at 1x ratio
RSVD
Reserved
mdio_pchan_5x Drive strength for P-channel at 5x ratio
mdio_pchan_1x Drive strength for P-channel at 1x ratio
Sticky
Bit Reset
Value
0h
02h
0h
0h
02h
0h
Bit Access
RV
RW
RW
RV
RW
RW
38.4.1.11 Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM
Ports 1 & 2
Table 38-13. Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM ports 1 &
2
Description: Drive Control of TDM port 1 & 2outputs
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:3:0
Offset Start: 00000068h
Offset End: 0000006Bh
Size: 32 bit
Default: 02000200h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 :28
27 :24
RSVD
Reserved
mdio_nchan_5x Drive strength for N-channel at 5x ratio
Sticky
Bit Reset
Value
0h
02h
Bit Access
RV
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1567