EP80579 Datasheet, PDF (755/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 19-29. Offset D8h: FDE: FWH Decode Enable Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: D8h
Offset End: DBh
Size: 16 bit
Default: FFCFh
Power Well: Core
Bit Range
08
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
EC0
LFE
LEE
Reserved
E70
E60
E50
E40
C0-C7 Enable: Enables decoding of 512K-Kbyte Firmware
Hub memory ranges:
0 = Disable.
1 = Enable the following ranges for the Firmware Hub:
Data space:FFC00000h – FFC7FFFFh
Feature space:FF800000h – FF87FFFFh
Legacy F Segment Enable: This enables the decoding of
the legacy 128K range at F0000h – FFFFFh
0 = Disable.
1 = Enable the following legacy ranges for the Firmware
Hub
F0000h – EFFFFh
Legacy E Segment Enable: This enables the decoding of
the legacy 128K range at E0000h – EFFFFh
0 = Disable.
1 = Enable the following legacy ranges for the Firmware
Hub
E0000h – EFFFFh
Reserved
70-7F Enable: Enables decoding of 1 MByte Firmware
Hub memory range:
Data space:FF700000h – FF7FFFFFh
Feature space:FF300000h – FF3FFFFFh
60-6F Enable: Enables decoding of 1 MByte Firmware
Hub memory range:
Data space:FF600000h – FF6FFFFFh
Feature Space:FF200000h – FF2FFFFFh
50-5F Enable: Enables decoding of 1 MByte Firmware
Hub memory range:
Data space:FF500000h – FF5FFFFFh
Feature space:FF100000h – FF1FFFFFh
40-4F Enable: Enables decoding of 1 MByte Firmware
Hub memory range:
Data space:FF400000h – FF4FFFFFh
Feature space:FF000000h – FF0FFFFFh
Bit Reset
Value
1
1
1
00h
1
1
1
1
Bit Access
RW
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
755