EP80579 Datasheet, PDF (1123/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.7
OCW2[0-1] - Operational Control Word 2 Register
Following a device reset or ICW initialization, the controller enters the fully nested
mode of operation. Non-specific EOI without rotation is the default. Both rotation mode
and specific EOI mode are disabled following initialization.
Table 30-12. OCW2[0-1] - Operational Control Word 2 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 020h, 0A0h
Offset End: 020h, 0A0h
Size: 8 bit
Default: 001XXXXXb
Power Well: Core
Bit Range
07 : 05
04 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
REOI
OCW2_SEL
INT_LS
Rotate and EOI Codes (R, SL, EO): These three bits
control the Rotate and End of Interrupt modes and
combinations of the two.
000
Rotate in Auto EOI Mode (Clear)
001
Non-specific EOI command
010
No Operation
011
*Specific EOI Command
100
Rotate in Auto EOI Mode (Set)
101
Rotate on Non-Specific EOI Command
110
*Set Priority Command
111
*Rotate on Specific EOI Command
*L0 - L2 Are Used
OCW2 Select: When selecting OCW2, bits 04:03 = “00”
Interrupt Level Select: L2, L1, and L0 determine the
interrupt level acted upon when the SL bit is active. A
simple binary code, outlined above, selects the channel for
the command to act upon. When the SL bit is inactive,
these bits do not have a defined function; programming
L2, L1 and L0 to 0 is sufficient in this case.
Code
Interrupt Level CodeInterrupt Level
000I
RQ0/8
100IRQ4/12
001
IRQ1/9
101IRQ5/13
010
IRQ2/10
110IRQ6/14
011
IRQ3/11
111IRQ7/15
Bit Reset
Value
001h
X
X
Bit Access
WO
WO
WO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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