EP80579 Datasheet, PDF (1048/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-3. Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register (Sheet 2 of
Description:
View: PCI
Size: 16 bit
BAR: Configuration
Default: 0200h
Bus:Device:Function: 0:31:0
Offset Start: A0h
Offset End: A0h
Power Well: Core^a
Bit Range Bit Acronym
Bit Description
Sticky
08
07
06
05
04
03
02
01 : 00
Reserved Reserved
Reserved Reserved
1 = Reserved
CPUSLP_EN
CPU SLP# Enable. Software sets this bit to enable the
CPUSLP# signal to go active in the S1 state.
0 = Disable.
1 = Enables the CPUSLP# signal to go active when the
processor is placed in S1 state. The signal is not
asserted when the EP80579 is in the S3, S4 or S5
state.
SMI_LOCK
When this bit is set, writes to the GLB_SMI_EN bit will have
no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e., once set, this bit can
only be cleared by PLTRST#).
RSVD
Reserved
RSVD
Reserved
Software sets these bits to control the rate at which the
periodic SMI# is generated:
00 = 64 seconds (default)
PER_SMI_SEL 01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
Tolerance for the timer is ±1 second.
a. Bits 10, 07:00 – Core; Bit 9 – Resume
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
00h
Bit Access
RW
RWO
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1048
August 2009
Order Number: 320066-003US