EP80579 Datasheet, PDF (874/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.1.2 Non-Queued DMA Data Transfers
The following sections describe a data transfer to and from a device using DMA as the
command type. These transfers are all non-queued.
23.5.1.2.1
ATA – Data from Memory to Device
Part I - Software Actions – Command Start
1. Software sets up a PRD table in memory, with one or more entries to accomplish
the data transfer of the full command. Software places the address for this table
PRD Base register.
2. Software writes to the task file to set up the command, with the final write being to
the command register (1F7h, 177h).
3. Software sets the “start” bit in the SATA host controller. This step can be swapped
with the previous step, since no action is taken until the data transfer is to begin.
Part II - Hardware Actions – Command Start
Upon seeing the command register written, hardware sends the register FIS to the
device, and awaits reception of a PIO setup FIS, device-to-host register FIS, DMA
Activate FIS, or DATA FIS.
Part III - Hardware Actions – Data Transfer
1. Since the direction of the transfer is from the host to the device (and the command
was a DMA command), hardware will receive a DMA Activate FIS.
2. Upon reception, if the ‘start’ bit has been set, hardware begins fetching data from
the locations specified in the PRD table. (Hardware could, and for performance
reasons should, have started fetching data prior to seeing the device-to-host
register FIS described in Part II).
3. Hardware formulates a DATA FIS and begins transmitting data to the device.
4. Hardware continues fetching PRDs as they become exhausted and fetching data
from PRD locations, until the transfer is complete. If the transfer is small enough,
this data may fall under a single DATA FIS. The SATA Host controller will send FISes
of maximum size to minimize FIS overhead on the data transfer.
Part IV - Hardware Actions – Command Wrap-Up
1. After the last piece of data has been accepted by the device, hardware awaits a
device-to-host register FIS.
2. When the register FIS is received, hardware updates its task file shadow block.
Part V - Software Actions – Command Wrap-Up
1. Reading device status and BMIDE status.
2. Complete request to OS.
3. Error handling may occur, including device reset & DMA engine re-initialization.
23.5.1.2.2 ATA – Data from Device to Memory
The ATA Device-to-Memory command is exactly the same as the ATA Memory-to-
Device command, except that in Part III, hardware is receiving DATA FISes and writing
data to memory, instead of fetching data from memory and sending DATA FISes. The
number of DATA FISes used is device specific. Additionally, a DMA Activate FIS will not
be received – the device will simply start sending a DATA FIS.
Intel^® EP80579 Integrated Processor Product Line Datasheet
874
August 2009
Order Number: 320066-003US