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EP80579 Datasheet, PDF (1494/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line
Intel® EP80579 Integrated Processor
Table 37-68. TIPG: Transmit IPG Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0410h
Offset End: 0413h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0410h
Offset End: 0413h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0410h
Offset End: 0413h
Size: 32 bits
Default: 00602008h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
19 : 10
09 : 00
Bit Acronym
Bit Description
Sticky
IPGR1
IPGT
IPG Receive Time 1.
Specifies the length of the first part of the IPG time for non
back-to- back transmissions. During this time, the internal
IPG counter restarts if any carrier event occurs. Once the
time specified in IPGR1 has elapsed, carrier sense does not
affect the IPG counter.
According to the IEEE802.3 standard, IPGR1 should be 2/3
of IPGR2 value. Measured in increments of the MAC clock:
• 8 ns MAC clock when operating @ 1 Gbps
• 80 ns MAC clock when operating @ 100 Mbps
• 800 ns MAC clock when operating @ 10 Mbps.
For IEEE 802.3 minimum IPG value of 96-bit time, the
value that should be programmed into IPGR1 is eight.
IPGR1 is significant only in half-duplex mode of operation.
IPG Transmit Time
Specifies the IPG time for back-to-back packet
transmissions
Measured in increments of the MAC clock:
• 8 ns MAC clock when operating @ 1 Gbps.
• 80 ns MAC clock when operating @ 100 Mbps.
• 800 ns MAC clock when operating @ 10 Mbps.
To calculate the IPG value for 10/100/1000BASE-T
applications, a value of four should be added to the IPGT
value as four clocks are used by the MAC as internal
overhead. The value that should be programmed into IPGT
is 8. These values are recommended to assure that the
minimum IPG gap is met under all synchronization
conditions.
Bit Reset
Value
0x8h
0x8h
Bit Access
RW
RW
Intel® EP80579 Integrated Processor Product Line Datasheet
1494
August 2009
Order Number: 320066-003US