EP80579 Datasheet, PDF (318/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
12.5.2
12.5.2.1
An example usage model for non-coherent accesses is management of data block areas
reserved for use by an EDMA-capable peripheral device, such as a network interface
controllers (NIC). The NIC writes data directly into a buffer in memory allocated for the
exclusive use of that device. Each EDMA channel would then execute a block transfer
from that buffer to an area allocated for IA-32 core use. Both integrity verification and
security functions executed by the IA-32 core could follow such a model. As long as
software ensures that the IA-32 core never traverses the device-allocated memory, the
block transfer could be accomplished using non-coherent source address reads followed
by coherent destination address writes.
I/O subsystem destination addresses are always treated as non-coherent or coherent
based on the bit setting in the DCR. Setting the destination coherency bit will result in
the PCI-Express snoop not required attribute bit being clear, snoop required.
Example: Setting BDF 010 Offset 2C DCRx register bit 7
Destination non-coherent = 0 => Snoop not required attribute bit = 1
Destination coherent = 1 => Snoop not required attribute bit = 0
Addressing Modes
Many different addressing modes are available, including standard byte movement
mode, byte reversal mode, constant address mode, and memory and buffer
initialization modes. In the examples shown for each of the following modes, a 64-bit
interface is used for simplicity. The interface could be the memory interface or an
external device on an expansion bus. Internally, the EDMA data path is significantly
wider.
Standard Byte Movement Mode
Standard byte movement mode is the most common method in which data is
transferred within the memory sub-system. In this mode, the source and destination
are specified down to the byte address. The source address is incremented as data is
read and the destination address is incremented as data is written. Transfers can be
memory to memory or memory to memory mapped I/O. Figure 12-5 illustrates a
memory to memory data transfer between unaligned 64-bit, source and destination
addresses.
Intel^® EP80579 Integrated Processor Product Line Datasheet
318
August 2009
Order Number: 320066-003US