EP80579 Datasheet, PDF (192/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-9. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
B8h
BCh
C4h
C6h
C8h
CAh
CCh
CEh
D8h
DEh
F6h
60h at 1h
70h at 4h
78h
64h
7Ch
84h
88h
8Ch
8Dh
90h
B0h
BBh
BFh
C5h
C7h
C9h
CBh
CDh
CFh
D8h
DFh
F6h
60h at 1h
73h at 4h
7Bh
67h
7Fh
87h
8Bh
8Ch
8Dh
93h
B3h
“Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register” on page 413
“Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register” on page 414
“Offset C4h: TOLM - Top of Low Memory Register” on page 415
“Offset C6h: REMAPBASE - Remap Base Address Register” on page 416
“Offset C8h: REMAPLIMIT – Remap Limit Address Register” on page 416
“Offset CAh: REMAPOFFSET - Remap Offset Register” on page 417
“Offset CCh: TOM - Top Of Memory Register” on page 417
“Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base
Address Register” on page 418
“Offset D8h: CACHECTL0 - Write Cache Control 0 Register” on page 418
“Offset DEh: SKPD - Scratchpad Data Register” on page 419
“Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register” on page 419
“Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register” on page 421
“Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register” on page 422
“Offset 78h: DRT0 - DRAM Timing Register 0” on page 424
“Offset 64h: DRT1 - DRAM timing Register 1” on page 431
“Offset 7Ch: DRC - DRAM Controller Mode Register” on page 435
“Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register” on
page 437
“Offset 88h: SDRC - DDR SDRAM Secondary Control Register” on page 439
“Offset 8Ch: CKDIS - CK/CK# Clock Disable Register” on page 441
“Offset 8Dh: CKEDIS - CKE Clock Enable Register” on page 442
“Offset 90h: SPARECTL - SPARE Control Register” on page 443
“Offset B0h: DDR2ODTC - DDR2 ODT Control Register” on page 444
Default
Value
000FFFFFh
00000000h
0800h
03FFh
0000h
0000h
0000h
E000h
00h
0000h
00h
ffh
00000515h
242AD280h
12110000h
00000002h
00000000h
00000002h
00h
00h
00000000h
00000000h
Table 7-10. Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers
Mapped Through NSIBAR Memory BAR (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
04h
08h
0Ch
10h
14h
1Ah
03h
07h
0Bh
0Dh
13h
17h
1Bh
“Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header
Register” on page 680
“Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1” on page 680
“Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2” on page 681
“Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register” on page 682
“Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register” on page 682
“Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register” on page 683
“Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register” on page 684
Default
Value
04010002h
00000000h
00000001h
0000h
00000001h
800000FFh
0002h
Intel^® EP80579 Integrated Processor Product Line Datasheet
192
August 2009
Order Number: 320066-003US