EP80579 Datasheet, PDF (1063/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.3.3.6
Note:
Offset 14h: LV2 - Level 2 Register
Reads to this register return all zeros, writes to this register have no effect. Reads to
this register generate a “enter a level 2 power state” (C2) to the clock control logic.
This will cause the STPCLK# signal to go active, and stay active until a break event
occurs. Throttling (due to THTL_EN or FORCE_THTL) will be ignored.
This register must not be used by systems with more than 1 logical processor, unless
appropriate semaphoring software has been put in place to ensure that all threads/
processors are ready for the C2 state when the read to this register occurs.
Table 27-16. Offset 14h: LV2 - Level 2 Register
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 14h
Offset End: 14h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
7 :0
Bit Acronym
Bit Description
LV2Reg
See description above
Sticky
Bit Reset
Value
00h
Bit Access
RO
27.3.3.7
Note:
Offset 28h: GPE0_STS - General Purpose Event 0 Status Register
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the STS bit is
set, a Wake Event is generated. Once back in an S0 state (or if already in an S0 state
when the event occurs), CMI will also generate an SCI if the SCIEN (PMBASE + 04h, bit
0) bit is set, or an SMI# if the SCIEN bit is not set. Bits 31:16 are reset by a CF9h
write; bits 15:0 are not be reset by CF9 write. Bits 31:0 are reset by RSMRST#.
Table 27-17. Offset 28h: GPE0_STS - General Purpose Event 0 Status Register (Sheet 1 of
4)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 28h
Offset End: 28h
Size: 32 bit
Default: 00000000h
Power Well: Resume
Bit Range
31 : 16
15
14
Bit Acronym
Bit Description
Sticky
GPIn_STS
Reserved
Reserved
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO
is set up as an input and the corresponding GPIO
signal is high (or low if the corresponding GP_INV
bit is set). If the corresponding enable bit is set in
the GPE0_EN register, then when the GPI[n]_STS
bit is set:
• If the system is in an S1, S3, S4 or S5 state, the
event will also wake the system.
• If the system is in an S0 state (or upon waking back
to an S0 state), an SCI will be caused, depending on the
GPI_ROUT bits for the corresponding GPI.
Reserved
Reserved.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1063