EP80579 Datasheet, PDF (905/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.3
Note:
Note:
SMBus Controller I/O-Mapped Configuration Register
Details
Warning: Address locations that are not listed are considered reserved register
locations. Reserved registers are read only and return all zeros.
For more information on the format of the register description tables that follow in this
chapter, see Section 7.1.1, “Register Description Tables” on page 183).
Table 24-18. Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration
Registers Mapped Through SM_BASE I/O BAR
Offset Start Offset End
Register ID - Description
00h
02h
03h
04h
05h
06h
07h
08h
0Ch
0Dh
0Eh
0Fh
00h
02h
03h
04h
05h
06h
07h
08h
0Ch
0Dh
0Eh
0Fh
“Offset 00h: HSTS: Host Status Register” on page 906
“Offset 02h: HCTL: Host Control Register” on page 908
“Offset 03h: HCMD: Host Command Register” on page 912
“Offset 04h: TSA: Transmit Slave Address Register” on page 912
“Offset 05h: HD0: Data 0 Register” on page 913
“Offset 06h: HD1: Data 1 Register” on page 913
“Offset 07h: HBD: Host Block Data Register” on page 914
“Offset 08h: PEC: Packet Error Check Data Register” on page 915
“Offset 0Ch: AUXS: Auxiliary Status Register” on page 915
“Offset 0Dh: AUXC: Auxiliary Control Register” on page 916
“Offset 0Eh: SMLC: SMLINK_PIN_CTL Register” on page 916
“Offset 0Fh: SMBC: SMBUS_PIN_CTL Register” on page 917
Default
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
07h
07h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
905