EP80579 Datasheet, PDF (726/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.4.7
18.4.8
18.4.9
18.4.10
Note:
Another option would be to build an A/D into the power supply itself. Another signal,
other than PWROK, could report that the power supply might soon fail.
Handling an ECC Error or Other Memory Error
The IMCH provides a message to indicate that it would like to cause an SMI#, SCI,
SERR#, or NMI. The software must check the IMCH as to the exact cause of the error.
SMM to Operating System and Operating System to SMM Calls
There may be interaction between an SMI handler and operating system-related code.
Two 8-bit data registers are provided.
1. The SMI handler generates an interrupt to the operating system by writing to the
TCO_DAT_OUT register. This sets the TCO_INT_STS bit in the TCO_STS register.
The interrupt is cleared by writing a one to the TCO_INT_STS bit.
2. The operating system (or driver) can generate an SMI# by writing to the
TCO_DAT_IN register. This sets the OS_SMI_STS bit in the TCO_STS register. The
SMI# is cleared by writing a one to the OS_SMI_STS bit.
Reads to the TCO_DAT_IN and TCO_DAT_OUT register do not effect the SMI# or
INTERRUPT.
Writing a one to the NMI_NOW bit allows for an immediate NMI.
Detecting an Improper FWH Programming
The CMI can detect the case where the FWH is not programmed. This results in the first
instruction fetched to have a value of FFh. If this occurs, the CMI sets the BAD_BIOS
bit.
IRQ1 and IRQ12 for Legacy Elimination
The new IRQ1 and IRQ12 sources are each logically ANDed with the respective IRQ1
and IRQ12 that come from the SERIRQ logic. This is necessary because the SERIRQ
logic reports IRQ1 and IRQ12 to be high (active), since there is no Super I/O to drive
them low.
In a system that does have a Super I/O, the new bits must be left at one, since it is
ANDed with the Super I/Os IRQ. Do not attempt to write these bits to 0 in a
system that has a keyboard controller (such as in a Super I/O). It is not
validated, and is highly likely to cause errors.
The following algorithm assumes the byte is being sent from the keyboard. The byte
being sent from the mouse is equivalent. The setup to the area of interest is left at a
high level in this description. The area of interest is then described in more detail.
1. An SMI is received and discovered to be a USB interrupt.
2. The interrupt is discovered to be due to a TD associated with a keyboard device.
3. The data is analyzed and it is determined that the interrupt is due to a new key
press.
4. The USB key-code is translated into the equivalent scan code set 2 (SS2) PS/2 scan
code.
5. The result is queued on a queue of data to be sent from the keyboard to the
system.
6. Other USB interrupts are handled.
Intel^® EP80579 Integrated Processor Product Line Datasheet
726
August 2009
Order Number: 320066-003US