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EP80579 Datasheet, PDF (289/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
11.0
11.1
11.2
System Memory Controller
Overview
The memory controller is responsible for controlling the off-chip DRAM devices. The
unit scheduler, control and protocol state machines access DRAM devices over a wide
range of speed bins using DDR2 DRAM technology. The EP80579 supports one memory
channel.
Memory Controller Feature List
The memory controller supports the following features
⢠Supports 1 DIMM
â DDR2
â 64 and 32-bit mode.
â Single rank (64 or 32-bit mode) or Dual rank (64 bit mode) device.
â DDR2-400, DDR2-533, DDR2-667, DDR2-800.
â See to âRules for Populating DIMM Slotsâ for more details.
⢠Supports dual DIMMs
â DDR2 and 64 bit mode only
â Registered Dual DIMM support with 1T command/address timing. Unbuffered
Dual DIMM support with 2T command/address timing. Please refer to â2T
Timing Modeâ for details.
â 32-bit mode dual DIMM is not supported
â Restrictions on speed, number of ranks and modes in 2 DIMM mode, refer to
âRules for Populating DIMM Slotsâ for details.
â DDR2-400 is supported.
â DDR2-533 and DDR2-667 are also supported with special design guidelines.
Refer to Table 11-5 for more details.
⢠Supports 32-bit mode
â 32-bit mode is for memory-down configuration, thus the following modes are
not supported: dual DIMM, dual rank, registered
⢠Supports 256 Mb, 512 Mb, 1 Gb and 2 Gb density parts in the x8 configuration.
Table 11-1 shows the various DDR2 device densities and widths supported.
Table 11-2 and Table 11-3 shows the various memory capacity configurations
supported using these parts in the 64 bit and 32-bit modes.
â Memory Controller does not support 4 Gb density
â See Section 11.3, âConfigurationsâ for more details.
⢠Supports 4-bank devices
â 256 Mb and 512 Mb DDR2 parts
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
289
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