EP80579 Datasheet, PDF (368/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 14-3. PCI Express Error Handling
Uncorrectable
Errors
IMCH specific
registers in dark grey
Correctable
Errors
N o n -fa ta l
Message
Fatal
Correctable
Message
Message
Adv. Error Capability &
Control
EXP_AERCACR
Header Log Register
E X P _H D R LO G [3:0]
Uncorrectable Error
Detect Mask
EXP_UNCERRDMSK
Mask on a
per bit basis
Uncorrectable Error Status
EXP_UNCERRSTS
Unsupport Request
All UNCs
Uncorrectable Error Mask
EXP_UNCERRMSK
All UNCs
UR UNCs
w/o UR
Uncorrectable Severity
EXP_UNCERRSEV
Uncorrectable Severity
EXP_UNCERRSEV
Device Status
EXP_DEVSTS
[3]
Device Control
EXP_DEVCTL
NFM
FM
Correctable Error Detect
Mask
EXP_CORERRDMSK
Mask on a
per bit basis
Correctable Error Status
EXP_CORERRSTS
Correctable Error Mask
EXP_CORERRMSK
F NF
C
SERRE
BCTRL[1]
RSE
SEC_STS[14]
Virtual &
Recieved
Message
Logic
SSE
PCISTS[14]
Correctable Error Ptr
EXP_ERRDOCMD
Error Source ID
EXP_ERRSID
1^st Error
Indicators
Root Error Cmd
EXP_RPERRCMD
Irpt Enable per type
Root Error Status
EXP_RPERRMSTS
1^st Error
Source IDs
MSI
Virtual Correctable Message
Virtual Non-fatal
Message
Virtual Fatal Message
Root Control
EXP_RPCTL
report enable
MSICAPA [0]
MSI enable
PCICMD[8]
Enable
SysERR
REPORT SELECT
EXP_ERRDOCMD
SERR
MCERR
SCI
SMI
Root Error Cmd
EXP_RPERRCMD
Irpt Enable per type
INTx
14.3
Error Conditions Signaled
The IICH-notification action taken by the IMCH upon detection of an error is controlled
through three registers. The SERRCMD register enables the generation of the SERR
message, the SCICMD register enables the generation of the SCI message, and the
SMICMD register enables the generation of SMI messages. Special cycle types of
DO_SERR, DO_SCI, or DO_SMI may be transmitted to the IICH. The IICH receives the
exception notification from the IMCH and may be configured to notify the processor of
the condition.
Once the processor has been interrupted, it polls the system to determine the cause of
the exception. If the IMCH initiated the exception condition by sending a message over
NSI, then the processor is so informed by the IICH. At this point, the processor may
read the IMCH’s error status registers to determine the exact cause of the condition.
The processor explicitly clears the status bit that points to the exception condition.
The IMCH in addition to signaling errors to the IICH for further handling, has added the
capability of signaling the processor directly by use of the front side bus error signal
MCERR#. The processor, upon observing this signal active, enters into special error
handling code known as machine check code.
Intel^® EP80579 Integrated Processor Product Line Datasheet
368
August 2009
Order Number: 320066-003US