EP80579 Datasheet, PDF (1436/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.1.1
Memory-Mapped Access to Internal Registers and Memories
The internal registers and memories may be accessed as direct memory-mapped
offsets from the base address register. See Section 37.6, “GbE Controller Register
Summary” for the appropriate offset for each specific internal register.
37.6.1.2
I/O-Mapped Access to Internal Registers and Memories
To support pre-boot operation (prior to the allocation of physical memory base
addresses), all internal registers and memories can be accessed using I/O operations.
I/O accesses are supported only if an I/O Base Address is allocated and mapped, the
BAR contains a valid (non-zero value), and I/O address decoding is enabled in the PCI/
PCIX configuration.
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte
“window” in the system I/O address map. Within this window, two I/O addressable
register are implemented: IOADDR and IODATA. The IOADDR register is used to
specify a reference to an internal register or memory and then the IODATA register is
used as a “window” to the register or memory address specified by IOADDR:
Table 37-24. I/O Mapped Registers
Offset
0x00
0x04
0x08 –
0x3F
Abbreviati
on
Name
R/W Size
IOADDR
Internal Register or Internal Memory Location Address.
0x00000-0x1FFFF – Internal Registers and Memories
0x20000-0xFFFFF – Undefined
RW 4 bytes
IODATA
Data field for reads or writes to the Internal Register or Internal
Memory Location as identified by the current value in IOADDR. All
32 bits of this register are read/write-able.
RW 4 bytes
Reserved Reserved
RW None
37.6.1.2.1 IOADDR (I/O offset 0x00)
The IOADDR register must always be written as a DWORD access (e.g. the
PCI_CBE_N[3:0] byte enables must all be enabled). Writes that are less than 32 bits
will be ignored. Reads of any size will return a DWORD of data. However, the chipset or
CPU may only return a subset of that DWORD.
For software programmers, the IN and OUT instructions must be used to cause I/O
cycles to be used on the PCI bus. Because writes must be to a 32-bit quantity, the
source register of the OUT instruction must be EAX (the only 32-bit register supported
by the OUT command). For reads, the IN instruction can have any size target register,
but it is recommended that the 32-bit EAX register be used.
Because only a particular range is addressable, the upper bits of this register are hard
coded to zero. Bits 31 through 20 are not write-able and always read back as 0b.
At hardware reset (LAN_PWR_GOOD) or PCI Reset, this register value resets to
0x00000000. Once written, the value is retained until the next write or reset.
37.6.1.2.2
IODATA (I/O offset 0x04)
The IODATA register must always be written as a DWORD access when the IOADDR
register contains a value for the Internal Register and Memories (e.g. 0x00000-
0x1FFFC). In this case, writes that are less than 32 bits will be ignored.
Writes and reads to IODATA when the IOADDR register value is in an undefined range
(0x20000-0x7FFFC) should not be performed. Results are indeterministic.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1436
August 2009
Order Number: 320066-003US