EP80579 Datasheet, PDF (1084/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Entry to Sleep states (S1, S3, S4 or S5) are initiated by any of the following methods:
1. Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field and setting the SLP_EN bit. The hardware will then put the
system into the corresponding Sleep state.
2. Pressing the PWRBTN# signal for more than four seconds to cause a Power Button
Override event. In this case the transition to the S5 state will be less graceful, since
there will be no dependencies on observing Stop-Grant cycles from the processor
or on clocks other than the RTC clock.
Other Assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor can only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
• Setting the SLP_EN bit will disable all throttling (since S1, S3, S4 or S5 sleep states
have higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power.
• Before entering sleep state, an ACPI OS will mask all interrupts and will turn off all
bus master enable bits. For non-ACPI systems, the BIOS will mask interrupts and
turn off all bus master enable bits. Interrupts might not be masked at the I/O
subsystem. Some Operating Systems have been observed to only mask interrupts
inside the processor.
Table 27-31. Sleep Types
Sleep Type
Comment
S1
CMI asserts the STPCLK# signal. It also has the option to assert CPUSLP# signal. This lowers
the processor’s power consumption. No snooping is possible in this state.
S3
CMI asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is
only retained to devices needed to wake from this sleeping state, as well as to the memory.
S4
CMI asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory
subsystem. Only devices needed to wake from this state should be powered.
S5
The SLP_S5# signal shuts off the power to the memory subsystem. Only devices needed to
wake from this state must be powered. CMI asserts SLP_S3#, SLP_S4# and SLP_S5#.
27.6.3
Note:
Exiting Sleep States
Sleep states (S1, S3, S4 or S5) are exited based on Wake events. The Wake events will
force the system to a full on state (S0), although some non-critical subsystems might
still be shut and have to be brought back manually. For example, the hard disk may be
shut during a sleep state, and have to be enabled via an I/O pin before it can be used.
Upon exit from CMI-controlled Sleep states, the WAK_STS bit will be set. To enable
Wake Events, the possible causes of wake events (and their restrictions) are shown in
Table 27-32.
There is no support for wake from USB when in S3/S4/S5.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1084
August 2009
Order Number: 320066-003US