EP80579 Datasheet, PDF (187/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Given the conventions outlined above, Table 7-4 presents an example definition for the
register EG_SINGLE which corresponds to a single physical register. This register
materializes at offset E0h in the configuration space for PCI device 4, at double-word
(i.e., 32-bit) offset 100h in the memory region defined by FOOBAR of PCI device 12,
and at the fixed offset 0A0h in IA I/O space¹.
Table 7-4. EG_SINGLE: Example Single Register with Different Views
Description: A single physical register that materializes at multiple locations.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: E0h
Offset End: E1h
View: PCI
BAR: FOOBAR
Bus:Device:Function: 0:12:0
Offset Start: 100h (4B)
Offset End: 101h (4B)
View: IA F Base Address: 0000h (IO)
Offset Start: A0h
Offset End: A1h
Size: 16 bit
Default: 8086h
Power Well: Core
Bit Range
15 : 00
Bit Acronym
Bit Description
Sticky
MAGIC
Magic Stuff: This field contains a magic number, 8086h.
Bit Reset
Value
8086h
Bit Access
RO
In the table, the materialization information includes the rows starting with “View” and
the title; the field definitions includes all rows below the row starting with “Bit Range”,
and the rows beginning “Description” and “Size” encompass the global information.
Table 7-5 presents an example definition for the register EG_MULTI_DIFF which
corresponds to two physical registers that materialize in different “devices”. The first
instance materializes at offset D0h in the configuration space for PCI device 20 and at
the fixed offset FFEF01B0h in IA memory space. The second instance materializes at
offset D0h in the configuration space for PCI device 21 and at the fixed offset
FFEF11C0h in IA memory space. Both registers have the same name, EG_MULTI_DIFF.
Table 7-5. EG_MULTI_DIFF: Example Multiple Registers in Different Devices with
Different Views
Description: A set of two physical registers that materialize in different devices.
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:20:0
Offset Start: D0h
Offset End: D3h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:21:0
Offset Start: D0h
Offset End: D3h
View: IA F 1 Base Address: 00000000h
Offset Start: FFEF01B0h
Offset End: FFEF01B3h
View: IA F 2 Base Address: 00000000h
Offset Start: FFEF11C0h
Offset End: FFEF11C3h
Size: 32 bit
Default: DEADBEEFh
Power Well: Core, Reset
Bit Range
31 : 00
Bit Acronym
Bit Description
BMAGIC Black Magic Stuff: This field contains a magic number.
Sticky
Bit Reset
Value
Bit Access
DEADBEEFh
RO
1. Recall that offsets are in bytes unless otherwise specified with “(2B)”, “(4B)”, or “(8B)”.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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