EP80579 Datasheet, PDF (113/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.2
3.2.1
IA Platform Infrastructure
The IMCH and IICH blocks (which, along with the IA-32 core, are collectively referred
to as the VCMI) in the EP80579 provide an IA platform infrastructure with respect to
endianness, address spaces and memory maps, configuration, etc.
This section focuses on the IA views and expectations around the endianness, address
spaces and memory maps, and configuration for a basic IA platform. The EP80579
operates within this framework. These discussions highlight how and where the
EP80579 differs from the framework. For additional detailed information on the IA
infrastructure in the EP80579 specifically, see Section 9.0, “CMI Introduction”, which
discusses the IMCH implementation.
IA Platform View of Endianness
All memory in an EP80579 platform is little-endian to match requirements and
expectations of an IA platform. The byte lanes (see Table 3-1 on page 112) are
connected from the memory interface to the IMCH such that little-endian IA-32 core
sees “byte 0” of a quad-word in memory in byte lane A and “byte 7” of a quad-word in
memory in byte lane H.
Consider the following C code:
char c, *cp;
// 1 byte
short s, *sp;
// 2 bytes
long l, *lp;
// 4 bytes
long long ll, *llp;
// 8 bytes
cp = sp = lp = llp = (void *) 0x8; // QW address 1
c = *cp;
s = *sp;
l = *lp;
ll = *llp;
Executing this code on the IA-32 core in an EP80579 yields the following results:
c == 8A
s == 8B8A
l == 8D8C8B8A
ll == 8H8G8F8E8D8C8B8A
Where the right-hand values in these results use the notation that Table 3-1 on
page 112 in Section 3.1.2 describes to identify the byte lanes and address.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
113