EP80579 Datasheet, PDF (196/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI
Configuration Registers (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
7Eh
E4h
E8h
80h
82h
84h
88h
8Ah
8Ch
8Eh
98h
9Ah
A0h
A4h
A8h
B0h
B2h
B4h
B6h
C2h
C4h
C6h
C8h
DCh
ECh
7Eh
E7h
EBh
81h
83h
84h
88h
8Ah
8Ch
8Eh
99h
9Bh
A3h
A7h
ABh
B1h
B3h
B5h
B7h
C3h
C5h
C7h
CBh
DDh
EFh
“Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register” on
page 480
00h
“Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register” on page 481 00040000h
“Offset E8h: BERRINJCTL - Buffer Error Injection Control Register” on page 482 00000000h
“Offset 80h: DRAM_FERR - DRAM First Error Register” on page 483
0000h
“Offset 82h: DRAM_NERR - DRAM Next Error Register” on page 484
0000h
“Offset 84h: DRAM_EMASK - DRAM Error Mask Register” on page 486
00h
“Offset 88h: DRAM_SCICMD - DRAM SCI Command Register” on page 487
00h
“Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register” on page 488
00h
“Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register” on page 489
00h
“Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register” on page 490 00h
“Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register” on page 491 0000h
“Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register” on page 491 0000h
“Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
Register” on page 492
00000000h
“Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register” on
page 492
00000000h
“Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register” on
page 493
00000000h
“Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register” on
page 494
0000h
“Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register” on
page 494
0000h
“Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register” on
page 494
0000h
“Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register” on
page 495
0000h
“Offset C2h: THRESH_DED - DED Error Threshold Register” on page 495
0000h
“Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct Syndrome
Register” on page 496
0000h
“Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register” on page 496
0000h
“Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register” on page 497
00000000h
“Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register” on page 498 0000h
“Offset ECh: DERRINJCTL - DRAM Error Injection Control Register” on page 499 00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
196
August 2009
Order Number: 320066-003US