EP80579 Datasheet, PDF (643/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-288.Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1 (Sheet 2
of 2)
Description: DDRIOMC1: DDRIO Mode Control Register 1
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 264h
Offset End: 267h
Size: 32 bit
Default: 52520000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
De-emphasis mode select bit for DQ/DQS pins. This mode
can be used to reduce power and enhance data eyes.
When de-emphasis is enable for a given group of I/Os,
subsequent driver values that are the same have their
strength reduced by half
It is recommended that this be controllable by the BIOS in
case there are unwanted side effects of this feature.
Bit Reset
Value
Bit Access
65
DEMPDQ
Encoding
00
01
10
Others
Description
Disabled
Weakly Enabled
Full Enabled
Reserved
Y
00b
RW
De-emphasis mode select bit for command/clock pins. This
mode can be used to reduce power and enhance data eyes.
When de-emphasis is enable for a given group of I/Os,
subsequent driver values that are the same have their
strength reduced by half.
It is recommended that this be controllable by the BIOS in
case there are unwanted side effects of this feature. For
instance, de-emphasis should be off before entering self-
refresh mode of the DRAM to prevent the CKE from
exceeding the JEDEC threshold once self-refresh is
entered.
43
DEMPCA
Encoding
00
01
10
Others
Description
Disabled
Weakly Enabled
Full Enabled
Reserved
Y
00b
RW
22
Reserved Reserved
10
FASTSLEW
bit[0] controls the control bits
bit[1] controls the data bits
Y
0b
RW
Y
00b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
643