EP80579 Datasheet, PDF (1534/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.7
37.6.7.1
Management Register Descriptions
WUC – Wake Up Control Register (0x05800; RW)
Table 37-131.WUC - Wake Up Control Register (0x05800; RW)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 5800h
Offset End: 5803h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 5800h
Offset End: 5803h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 5800h
Offset End: 5803h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 04
03
02
01
00
Bit Acronym
Bit Description
Sticky
RSVD
Reserved
APMPME
Assert PME On APM Wakeup –
If it is 1, the GbE will set the PME_Status bit in the Power
Management Control / Status Register (PMCSR) and assert
GBE_PME_WAKE when APM Wakeup is enabled and the
GbE receives a matching magic packet.
*Note that this bit is loaded from the EEPROM, if present
PME_Status
PME_Status
This bit is set when the GbE receives a wakeup event. It is
the same as the PME_Status bit in the Power Management
Control / Status Register (PMCSR). Writing a “1” to this bit
will clear it and clear the PME_Status bit in the PMCSR.
PME_EN
PME_En
This read/write bit is used by the driver to access the
PME_En bit of the Power Management Control / Status
Register (PMCSR) without writing to PCI configuration
space.
APME
Advance Power Management Enable -
If “1”, APM Wakeup is enabled.
*Note that this bit is loaded from the EEPROM, if present
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RW
RWC
RW
RW
Note: The PME_En and PME_Status bits are reset when PWR_GOOD is 0. When
AUX_PWR_PRESENT=0, this register is also reset by the deassertion (rising edge) of
RESET_N and the transition from D3 to D0. The other bits are reset on the standard
internal resets.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1534
August 2009
Order Number: 320066-003US