EP80579 Datasheet, PDF (1178/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-13. Offset 01h: IER - Interrupt Enable Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO) (DLAB = 0)
Offset Start: 01h
Offset End: 01h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
RLSE
TIE
RAVIE
Receiver Line Status Interrupt Enable:
0 = Receiver Line Status interrupt disabled
1 = Receiver Line Status interrupt enabled
Transmit Data request Interrupt Enable:
0 = Transmit FIFO Data Request interrupt disabled
1 = Transmit FIFO Data Request interrupt enabled
Receiver Data Available Interrupt Enable:
When BIT 5 = 1:
0 = Receiver Data Available (Trigger level reached)
interrupt disabled
1 = Receiver Data Available (Trigger level reached)
interrupt enabled
When BIT 5 = 0:
0 = Receiver data Time Out Interrupt also disabled
1 = Receiver data Time Out Interrupt enabled
Sticky
Bit Reset
Value
Bit Access
0h
RW
0h
RW
0h
RW
33.5.3.4
Offset 02h: IIR - Interrupt Identification Register
In order to minimize software overhead during data character transfers, the UART
prioritizes interrupts into four levels (listed in Table 33-14) and records these in the
Interrupt Identification Register. The Interrupt Identification Register (IIR) stores
information indicating that a prioritized interrupt is pending and the source of that
interrupt.
Table 33-14. Interrupt Conditions
Priority
Level
Interrupt Origin
1 (highest)
2
2
3
4
Receiver Line Status. One or more error bits were set.
Received Data is available. In FIFO mode, trigger level was reached; in non-FIFO mode, RBR
has data.
Receiver Time out occurred. It happens in FIFO mode only, when there is data in the receive
FIFO but no activity for a time period.
Transmitter requests data. In FIFO mode, the transmit FIFO is half or more than half empty; in
non-FIFO mode, THR is read already.
Modem Status: one or more of the modem input signals has changed state
Intel^® EP80579 Integrated Processor Product Line Datasheet
1178
August 2009
Order Number: 320066-003US