EP80579 Datasheet, PDF (216/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.11
SMBus Controller: Bus 0, Device 31, Function 3
The SMBus controller includes the registers listed in Table 7-30 and Table 7-31. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR),
respectively. See Chapter 24.0, “SMBus Controller Functional Description: Bus 0,
Device 31, Function 3” for detailed discussion of these registers.
Table 7-30. Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration
Registers
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
09h
0Ah
0Bh
20h
2Ch
2Eh
3Ch
3Dh
40h
F8h
01h
03h
05h
07h
08h
09h
0Ah
0Bh
23h
2Dh
2Fh
3Ch
3Dh
40h
FBh
“Offset 00h: VID: Vendor ID Register” on page 897
“Offset 02h: DID: Device ID Register” on page 897
“Offset 04h: CMD: Command Register” on page 897
“Offset 06h: DS – Device Status Register” on page 898
“Offset 08h: RID: Revision ID Register” on page 899
“Offset 09h: PI: Programming Interface Register” on page 900
“Offset 0Ah: SCC: Sub Class Code Register” on page 900
“Offset 0Bh: BCC: Base Class Code Register” on page 900
“Offset 20h: SM_BASE: SMB Base Address Register” on page 901
“Offset 2Ch: SVID: SVID Register” on page 901
“Offset 2Eh: SID: Subsystem Identification Register” on page 902
“Offset 3Ch: INTLN: Interrupt Line Register” on page 902
“Offset 3Dh: NTPN: Interrupt Pin Register” on page 903
“Offset 40h: HCFG: Host Configuration Register” on page 903
“Offset F8h: MANID: Manufacturer ID Register” on page 904
Default
Value
8086h
5032h
0000h
0280h
Variable
00h
05h
0Ch
00000001h
0000h
0000h
00h
Variable
00h
00010F90h
Table 7-31. Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration
Registers Mapped Through SM_BASE I/O BAR
Offset Start Offset End
Register ID - Description
00h
02h
03h
04h
05h
06h
07h
08h
0Ch
0Dh
0Eh
0Fh
00h
02h
03h
04h
05h
06h
07h
08h
0Ch
0Dh
0Eh
0Fh
“Offset 00h: HSTS: Host Status Register” on page 906
“Offset 02h: HCTL: Host Control Register” on page 908
“Offset 03h: HCMD: Host Command Register” on page 912
“Offset 04h: TSA: Transmit Slave Address Register” on page 912
“Offset 05h: HD0: Data 0 Register” on page 913
“Offset 06h: HD1: Data 1 Register” on page 913
“Offset 07h: HBD: Host Block Data Register” on page 914
“Offset 08h: PEC: Packet Error Check Data Register” on page 915
“Offset 0Ch: AUXS: Auxiliary Status Register” on page 915
“Offset 0Dh: AUXC: Auxiliary Control Register” on page 916
“Offset 0Eh: SMLC: SMLINK_PIN_CTL Register” on page 916
“Offset 0Fh: SMBC: SMBUS_PIN_CTL Register” on page 917
Default
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
07h
07h
Intel^® EP80579 Integrated Processor Product Line Datasheet
216
August 2009
Order Number: 320066-003US