EP80579 Datasheet, PDF (346/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 13-1. PCI Devices and Functions on Bus 0
Device
0
0
1
2
8
31
31
31
31
31
29
29
Function
0
1
0
0
0
0
2
3
5
6
0
7
Function Description
IMCH
IMCH, error status
IMCH EDMA engine
IMCH PCI Express Port A0 X8 or X4 unit
IMCH Test and Device 0 Overflow
IICH LPC Interface
IICH SATA Controller
IICH SMBus Controller
Reserved
Reserved
IICH USB Controller #1
IICH USB 2.0 Controller
13.2.1 IMCH PCI Devices
The PCI predefined header has five fields that deal with device identification. All devices
are required to implement these fields. Generic configuration software is able to easily
determine the device available for use. These registers are read only. The five fields are
vendor ID, device ID, revision ID, header type, and class code:
• The 16-bit vendor ID is assigned by PCI SIG and has a value of 8086h for Intel.
• The 16-bit device ID is assigned by the vendor.
• The 8-bit revision ID is chosen by the vendor to indicate the different steppings of a
device. The value 00h designates an A0 stepping. The value 01h designates an B0
stepping.
• The header type specifies the structure of the second half of the header, and also
whether or not the device has multiple functions. The value 80h indicates a multi-
function device.
• The class-code field identifies the generic function of the device. The class-code is
further broken into three sub-fields, base class, sub-class, and programming
interface. CMI proper has a base class code of 06h indicating a bridge device. The
sub-class value of 00h indicates a host bridge.
A disabled or non-existent IMCH device’s configuration register space is hidden,
returning all 1’s for reads and dropping writes just as if the cycle terminated with a
Master Abort on PCI.
If one or more IICH devices or some of their functions are not supported on the
platform, each can be disabled individually. When a device or function is disabled, it
does not appear at all to the software: No responses to any register reads and no
responses to any register writes. This is intended to prevent software from thinking
that a device or function is present (and reporting it to the end-user).
When a PCI Express interface is unpopulated or fails to train, the associated
configuration register space is hidden, returning all ones for all registers just as if the
cycle terminated with a Master Abort on PCI. Also, if PCI Express port PEA0 is
configured for x8 operation rather than x4, the corresponding PCI Express port PEA1
configuration space will be hidden.
Intel^® EP80579 Integrated Processor Product Line Datasheet
346
August 2009
Order Number: 320066-003US