EP80579 Datasheet, PDF (724/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
18.4.2
18.4.3
Detecting a DOA CPU or System
When the processor is reset, it is expected to fetch its first instruction. If the processor
fails to fetch the first instruction after reset, the TCO timer times out twice and CMI
asserts PLTRST#.
If TCO Reboots are not enabled, then:
a. The SMLink sends out the first eight bits of the message. After the eighth bit,
the logic stalls because there is no integrated LAN controller to send the ACK.
The logic then aborts the transfer. External logic monitors the toggling and use
that to drive an LED.
b. If an External LAN controller is connected send the appropriate message to the
External LAN controller.
If TCO Reboots are enabled, then the CMI attempts to reboot the system.
1. If the NO-REBOOT bit (NR field in Table 17-27, “Offset 3410h: GCS - General
Control and Status Register” on page 706) is set (no reboots are intended)
and
SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is set
and
DOACPU_STS bit (TCO I/O Offset 06h, bit 2) is set,
then the CMI indicates this in the TCO message by setting the CPU Missing bit in the
message.
2. If the NO-REBOOT bit (NR field in Table 17-27, “Offset 3410h: GCS - General
Control and Status Register” on page 706) is not set (reboots intended)
and
SECOND_TO_STS bit TCO I/O Offset 06h, bit 1) is set,
then the CMI attempts to reboot. After the reboot, the SECOND_TO_STS bit is still set.
If the CPU fails to fetch the first instruction, the DOA_CPU_STS bit is set, and when the
TCO timer times out (actually for the third time, the first two caused the
SECOND_TO_STS bit to be set), then the CMI sets the CPU MISSING EVENT bit for the
TCO message.
Handling an Operating System Lockup
Under some conditions, the operating system may lock up. To handle this, the TCO
Timer is used with the following algorithm:
1. BIOS programs the TCO Timer, via the TCO_TMR register with an initial value.
2. An operating system-based software agent periodically writes to the TCO_RLD
register to reload the timer and keep it from generating the SMI#. The software
agent can read the TCO_RLD register to see if it is close to timing out, and possibly
determine if the time-out should be increased. The operating system can also
modify the values in the TCO_TMR register.
3. If the timer reaches 0, an SMI# can be generated. This should only occur if the
operating system was not able to reload the timer. It is assumed that the operating
system is not able to reload the timer if it has locked up.
4. Upon generating the SMI#, the TCO Timer automatically reloads with the default
value of 04h and start counting down.
Intel^® EP80579 Integrated Processor Product Line Datasheet
724
August 2009
Order Number: 320066-003US