EP80579 Datasheet, PDF (580/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.65 Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register
This register contains the first 32 bits of the header log locked down when the first
uncorrectable error occurs that saves the header. To rearm this register all report
uncorrectable errors must be cleared from the register. Software after clearing the
errors must read the register again to ensure that it is indeed cleared. If it finds that
another error occurred, it can not rely on the pointer or header, unless it detects that
the error pointer changed from the last time it was read for the previous error. Byte 0
of the header is located in byte 3 of the Header Log Register 0, byte 1 of the header is
in byte 2 of the Header Log Register 0 and so forth. For 12 byte headers, only the first
three of the four Header Log Registers are used, and values in HDRLOG3 are undefined.
These bits are sticky through reset.
Table 16-204. Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 11Ch
Offset End: 11Fh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 11Ch
Offset End: 11Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Header Log 0 A masked error (respective bit set to ‘1’ in
HL0
mask register) is not logged in the Header Log Register,
does not update the First Error Pointer, and is not reported
Y
to the PCI Express* Root Complex by an individual device.
Bit Reset
Value
00000000h
Bit Access
RO
16.4.1.66 Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register
The function of the Header Log registers is described in Section 16.4.1.65, “Offset
11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register”. Header Log DW1 contains
the second 32 bits of the header. Byte 4 of the header is located in byte 3 of the Header
Log Register 1, byte 5 of the header is in byte 2 of the Header Log Register 1 and so
forth. These bits are sticky through reset.
Table 16-205.Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 120h
Offset End: 123h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 120h
Offset End: 123h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
Header Log 1 A masked error (respective bit set to ‘1’ in
mask register) is not logged in the Header Log Register,
HL1
does not update the First Error Pointer, and is not reported Y
to the PCI Express* Root Complex by an individual device.
These bits are sticky through system reset.
Bit Reset
Value
00000000h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
580
August 2009
Order Number: 320066-003US