EP80579 Datasheet, PDF (948/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.1.1.12 INTL - Interrupt Line Register
Table 25-13. INTL - Interrupt Line Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
INTL
Interrupt line: This data is not used. This data is used to
communicate to software which interrupt line the interrupt
pin is connected to.
Bit Reset
Value
00h
Bit Access
RW
25.1.1.13 INTP - Interrupt Pin Register
Table 25-14. INTP - Interrupt Pin Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 3Dh
Offset End: 3Dh
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
INTPN
Interrupt Pin: This read-only value tells the software
which interrupt pin each USB host controller uses. The
upper 4 bits are hardwired to 0000b; the lower 4 bits are
determine by the Interrupt Pin default values that are
programmed in the memory-mapped configuration space
as follows:
Function 0
D29IP.U0P
Note: This does not determine the mapping to the PIRQ
pins.
Bit Reset
Value
Variable
Bit Access
RO
25.1.1.14 SBRN - Serial Bus Release Number Register
A value of 10h indicates that this is controller follows USB release 1.1.
Table 25-15. SBRN - Serial Bus Release Number Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:0
Offset Start: 60h
Offset End: 60h
Size: 8 bit
Default: 10h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
SBN
Indicates that this controller follows USB release 1.0.
Sticky
Bit Reset
Value
10h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
948
August 2009
Order Number: 320066-003US