EP80579 Datasheet, PDF (1456/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-37. ICR0: Interrupt 0 Cause Read Register (Sheet 3 of 3)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 00C0h
Offset End: 00C3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 00C0h
Offset End: 00C3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 00C0h
Offset End: 00C3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Rsvd
RXDMT0
Rsvd
Rsvd
TXQE
TXDW
Reserved
Receive Descriptor Minimum Threshold Hit. Indicates
that the minimum number of receive descriptors are
available and software should load more receive
descriptors.
Reserved
Reserved
Transmit Queue Empty. Set when the last descriptor
block for a transmit queue has been used.
Transmit Descriptor Written Back. Set when hardware
processes a descriptor with its RS bit set. If using delayed
interrupts (TDESC.IDE is set in the Transmit Descriptor
CMD), the interrupt is delayed until after one of the
delayed-timers (TIDV or TADV) expires.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
Bit Access
RV
RCWC
RCWC
RV
RCWC
RCWC
Intel^® EP80579 Integrated Processor Product Line Datasheet
1456
August 2009
Order Number: 320066-003US