EP80579 Datasheet, PDF (146/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 5-6.
Summary of IMCH NSI Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
Received
Correctable Error
Message
Parity Error on
Data from Core
Correctable
Uncorrectable
Link Down
Uncorrectable
Non-Fatal
Non-Fatal
Fatal
SCI, MCERR, Correctable error message received
SMI, or SERR over NSI link.
SCI, MCERR, Parity error detected on data received
SMI, or SERR from core.
SCI, MCERR, Link transitioned from DL_UP to
SMI, or SERR DL_DOWN.
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD register values.
Table 5-7 summarizes the capabilities of the NSI error handling for each of the features
that the unit is expected to provide.
Table 5-7.
Summary of IMCH NSI Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The NSI_EMASK, NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD
registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
NSI captures error logging information in the following registers:
• All errors: NSI_FERR, NSI_NERR, and PCISTS capture event flags.
• Poisoned TLP: PCISTS captures event flags.
• Received fatal/non-fatal/correctable error messages: NSI_ERRSID.
All of the logging information that the NSI captures relates to the “first” error with the
exception of NSI_NERR.
Reporting Multiple The NSI_NERR register captures “next” errors. This register indicates up to one additional
Errors
error (beyond the first error) of each type.
Data Poisoning NSI passes along error information to poison data.
For additional discussion on the IMCH responses to transactions from the NSI interface,
see Section 10.1, “Overview”.
5.3.7
Unit-Level Errors from the EDMA Engine
The IMCH EDMA unit captures error events from the EDMA engine in the EDMA_FERR
and EDMA_NERR registers (The EDMA unit reports an error event to the IA-32 core
through IA SCI, SMI, SERR, or MCERR signals based on the settings in the
EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD registers.
Software can independently configure the specific signal that each EDMA unit error
event uses.
.
Table 5-8.
Table 5-8 summarizes the error conditions that the EDMA can generate.
Summary of IMCH EDMA Error Conditions
Event
Type
Fatality^a
Reports via^b
Notes
NDAR Addressing
Error
NDAR Alignment
Error
Source Address
Error
Uncorrectable
Uncorrectable
Uncorrectable
Non-Fatal
Non-Fatal
Non-Fatal
SCI, MCERR, Descriptor pointer is of incorrect type
SMI, or SERR or range for channels 0-3.
SCI, MCERR, Descriptor pointer is not aligned to an
SMI, or SERR 8 DW boundary for channels 0-3.
SCI, MCERR, Source address does not comply with
SMI, or SERR source type or range for channels 0-3.
Intel^® EP80579 Integrated Processor Product Line Datasheet
146
August 2009
Order Number: 320066-003US