EP80579 Datasheet, PDF (262/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
9.5.4
9.5.5
9.5.6
• Increment of the source and destination address for standard transfers
• Increment of the destination and decrement of the source address to enable byte
stream reversal.
• Constant address mode for the destination address based on the transfer
granularity to enable targeting of memory mapped I/O FIFO devices
• Buffer/Memory Initialization Mode
Coherent Memory Write Buffer
• Support for 16 64-byte cache-lines of write data
• Fully associative conflict detection for accesses targeting memory
• Read around write support (non-conflicting) for all traffic to memory
• Read-hit support for CPU traffic to memory
— Direct data service from buffer without generation of memory traffic
• Write-hit support for memory traffic with address conflicts
— Hardware-based merging to collapse down to a single memory write
• Opportunistic and demand (buffer full) mode processing of pending writes
— Configurable “watermark” mechanism for hardware-based prioritization
— Flush on demand via software configuration mechanism
• Parity protection on all data
• Data poisoning capability in the main store for data received with errors
• Processor writes to shared non-coherent address space with the ASU result in a
flush of the current cacheline to main memory
• ASU atomics will result in a DW write to the ASU out of the write cache
Integrated Memory Scrub Engine
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
• Periodic (programmable) read-modify-write algorithm
• Support for the SEC-DED mode of operation
• Automatic correction of encountered SEC errors
• Logging of detected errors with granularity to isolate DRAM device
— Support for logging of both first and next subsequent error
— Count of errors beyond the first two which are logged
• Support for on-demand hardware scrub of SEC errors detected during normal
operation
• Programming interface permits software suspend/resume of scrub in progress
Hardware Memory Initialization Engine
• Available via BIOS for hardware memory initialization and/or test
• Provides fast WHQL initialization of all populated DRAM space to “0” with good ECC
• Target region may be a single location, an entire rank, or all populated ranks
• Algorithm optimized for speed, runs at DDR channel saturation rate
Intel^® EP80579 Integrated Processor Product Line Datasheet
262
August 2009
Order Number: 320066-003US