EP80579 Datasheet, PDF (1543/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-142.FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 9000h at 8h
Offset End: 9003h at 8h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 9000h at 8h
Offset End: 9003h at 8h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 9000h at 8h
Offset End: 9003h at 8h
Size: 32 bits
Default: 0000000Xh
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 04
03 : 00
RSVD
Mask_x
Reserved
Byte Mask for Byte xx
Sticky
Bit Reset
Value
0h
Xh
Bit Access
RV
RW
Note:
Before writing to the Flexible Filter Length Table the driver must first disable the flexible
filters by writing 0's to the Flexible Filter Enable bits of the Wake Up Filter Control
Register (WUFC.FLXn)
37.6.7.12 FFVT[0-127] – Flexible Filter Value Table Registers
The Flexible Filter Value and Table is used to store the one value for each byte location
in a packet for each flexible filter. If the corresponding mask bit is 1, the Flexible Filter
will compare the incoming data byte to the values stored in this table.
Table 37-143.Flexible Filter Mask Table
Address
0x9800
0x9808
0x9810
...
0x9BF8
Content
Byte 0 Values
Byte 1 Values
Byte 2 Values
Byte 3 - 126
Values
Byte 127 Values
Address
0x9804
0x980C
0x9814
...
0x9BFC
Content
Reserved
Reserved
Reserved
Reserved
Reserved
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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