EP80579 Datasheet, PDF (880/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Each of these device states are subsets of the host controller’s D0 state. This is partially
because host controllers (as integrated in Intel components) have not supported host-
based power management, and also because the device must be put into one of the
lower power states before power could be removed from the host.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings
to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active.
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than
10µs.
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to
10ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA Controller defines these states as sub-states of the device D0 state.
Figure 23-1 is an hierarchical view of SATA power states.
Figure 23-1. Legacy Mode Host Controller Power State Hierarchy
Power
PHY =
R ead y
Host = D0
Device = D0
PHY =
Partial
PHY = PHY =
Slumb er Off (port
dis abled)
Device = D1
PHY = PHY =
Slumber Off (port
dis ab led)
Device = D3
PHY = PHY =
Slumber Off (port
disabled)
Host = D3
Device = D3
PHY =
OF F
Resume Latency
23.5.5.3 Power State Transitions
Transitioning between various states is initiated by different levels of software and
hardware.
23.5.5.3.1 Partial and Slumber State Entry/Exit
The partial and slumber states are viewed as cheap and easy mechanism to save
interface power when the interface is idle. The SATA Controller defines PHY layer power
management (as performed via primitives) as a driver operation from the host side,
and a device proprietary mechanism on the device side. The SATA Controller will accept
device transition types, but will not issue any transitions as a host. All received
requests from an SATA device will be ACKed.
When an operation is performed to the SATA Controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
Intel^® EP80579 Integrated Processor Product Line Datasheet
880
August 2009
Order Number: 320066-003US