EP80579 Datasheet, PDF (1618/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Register Name:
SSDR
Block
Base Address:
N/A
Offset Address
0x10
Reset Value
00000000
Register Description: SSP Data Register
Access: (See below.)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Data
Table 40-7. Offset 10h: SSDR - SSP Data Register Details
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:6:0
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :16
15 :00
Bit Acronym
Bit Description
Sticky
Reserved
Data
Reserved
Data (Low Word): When written, the data will be written
to the Transmit FIFO.
When read, data from the Receive FIFO is returned.
Bit Reset
Value
0h
0h
Bit Access
RV
RW
§§
Intel^® EP80579 Integrated Processor Product Line Datasheet
1618
August 2009
Order Number: 320066-003US