EP80579 Datasheet, PDF (119/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
3.4
Memory Map for IA-Attached Agents
There are two constraints in the EP80579 CMI and Memory Controller designs:
• The IA-32 core only supports 32-bit physical addresses.
• The Memory Controller supports at most 4GB of physical memory.
This discussion focuses on the perspective of an IA-attached agent; Section 3.5,
“Memory Map for AIOC-Attached Devices” on page 119 provides similar discussion for
AIOC-attached agents.
Table 3-6.
Device Exposure from an IA-attached Memory Map Perspective
Device to Access
PCIe GigE MACs
IMCH/IICH AIOC
devices
DRAM
Materializes
In Region
Notes
PCI L
DRAM AD
DRAM C
• PCI BAR(s) set by IA O/S or BIOS specify address mapping(s).
• IA-32 core configures through I/O or PCI enhanced config spaces.
• Reads, config space access between I/O agents not supported.
• Region is at least 128MB per definition of TOLM, see Section
16.1.1.30, “Offset C4h: TOLM - Top of Low Memory Register”.
• Contains IA/ASU Shared (AIOC-Direct) region from Table 3-3.
• MENCBASE and MENCLIMIT registers define address range.
• IA caches not coherent with AIOC accesses to this region.
• Must include all DRAM that is inaccessible to the IA-32 core.
• Contains I/A O/S, IA/ASU Shared (Coherent) regions from
Table 3-3.
• IA caches coherent with AIOC accesses to this region.
• Cannot include any DRAM that is inaccessible to the IA-32 core.
3.5
Memory Map for AIOC-Attached Devices
AIOC-attached agents support several independent target IDs that provide
independent address spaces. Table 3-7 summarizes, the addressing capabilities of
AIOC agents range from 25 to 32-bits.
Table 3-7.
Address Space Sizes of AIOC-attached Devices
Address Space Size [b]
32
32
Devices
Gigabit Ethernet MACs
ASU, SSU, TDM, SSP, CAN, 1588
3.6
Endianness
The EP80579 operates in an IA platform environment that is little-endian.
3.7
PCI Configuration
This section presents an overview of the implementation that integrates the AIOC and
memory controller with the IA PCI infrastructure for configuration.
• PCI mechanisms (configuration space, memory-mapped I/O spaces, and I/O
spaces) expose state for configuration.
• The IA-32 core performs all system configuration and initialization.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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