EP80579 Datasheet, PDF (1465/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-43. ICS1: Interrupt 0 Cause Set Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08C8h
Offset End: 08CBh
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08C8h
Offset End: 08CBh
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08C8h
Offset End: 08CBh
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
22
21
20
19 : 17
16
15
14 : 8
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Rsvd
ERR_TXDS
ERR_RXDS
Rsvd
SRPD
TXD_LOW
Rsvd
RXT0
RXO
Rsvd
RXDMT0
Rsvd
Rsvd
TXQE
TXDW
Reserved
Triggers DMA Transmit Descriptor Buffer ECC Error
Triggers DMA Receive Descriptor Buffer ECC Error
Reserved
Triggers Small Receive Packet Detected and Transferred
Triggers Transmit Descriptor Low Threshold Hit
Reserved
Triggers Receiver Timer Interrupt
Triggers Receiver Overrun. Set on receive data FIFO
overrun
Reserved
Triggers Receive Descriptor Minimum Threshold hit
Reserved
Reserved. Must be written as ‘0’
Triggers Transmit Queue Empty
Triggers Transmit Descriptor Written Back
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RW
RV
RW
RW
RV
RW
RW
RV
RW
RV
RV
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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