EP80579 Datasheet, PDF (963/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-28. PSCR - Port Status and Control Register (Sheet 2 of 2)
Description:
View: PCI 1
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start:^a 10h
Offset End: 11h
View: PCI 2
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 12h
Offset End: 13h
Size: 16 bit
Default: 0080h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
06
05 : 04
03
02
01
00
RSM_DET
LNS
PORT_ENC
PORT_EN
CSC
CCS
Resume Detect:
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Software sets this bit to a 1 to drive resume signaling.
The Host Controller sets this bit to a 1 if a J-to-K
transition is detected for at least 32 µs while the port is
in the Suspend state. CMI will then reflect the K-state
back onto the bus as long as the bit remains a ‘1’, and
the port is still in the suspend state (bit 12,2 are ‘11’)
Writing a 0 (from 1) causes the port to send a low speed
EOP. This bit will remain a 1 until the EOP has
completed.
Line Status: These bits reflect the D+ (bit 4) and D-
(bit 5) signals lines logical levels. These bits are used for
fault detect and recovery as well as for USB diagnostics.
This field is updated at EOF2 time.
Port Enable/Disable Change:
0 = No change.
1 = Port enabled/disabled status has changed.
For the root hub, this bit gets set only when a port is
disabled due to disconnect on the that port or due to the
appropriate conditions existing at the EOF2 point (See
the USB Specification). Software clears this bit by
writing a 1 to it.
Port Enabled/Disabled:
0 = Disable.
1 = Enable.
Ports can be enabled by host software only. Ports can be
disabled by either a fault condition (disconnect event,
overcurrent, or other fault condition) or by host
software. The bit status does not change until the port
state actually changes and that there may be a delay in
disabling or enabling a port if there is a transaction
currently in progress on the USB.
Connect Status Change:
0 = No change.
1 = Change in Current Connect Status.
Indicates a change has occurred in the port’s Current
Connect Status (see bit 0). The hub device sets this bit
for any changes to the port device connect status, even
if system software has not cleared a connect status
change. If, for example, the insertion status changes
twice before system software has cleared the changed
condition, hub hardware will be “setting” an already-set
bit (i.e., the bit will remain set). However, the hub
transfers the change bit only once when the Host
Controller requests a data transfer to the Status Change
endpoint. System software is responsible for
determining state change history in such a case.
Software sets this bit to 0 by writing a 1 to it.
Current Connect Status:
0 = No device is present.
1 = Device is present on port.
This value reflects the current state of the port, and may
not correspond directly to the event that caused the
Connect Status Change bit (Bit 1) to be set.
a. USB #1 Port 0: 10-11hPort 1: 12-13h
Bit Reset
Value
0h
00h
0h
0h
0h
0h
Bit Access
RW
RO
RWC
RW
RWC
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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