EP80579 Datasheet, PDF (991/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.20 Offset 58h: DP_CID - Debug Port Capability ID Register
Table 26-22. Offset 58h: DP_CID - Debug Port Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 58h
Offset End: 58h
Size: 8 bit
Default: 0Ah
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
DP_CID
This register is hardwired to 0Ah which indicates that this
is the start of a Debug Port Capability structure.
Bit Reset
Value
0Ah
Bit Access
RO
26.2.1.21 Offset 59h: DP_NEXT - Next Item Pointer #2 Register
Table 26-23. Offset 59h: DP_NEXT - Next Item Pointer #2 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 59h
Offset End: 59h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
DP_NEXT
This register is hardwired to 00h, which indicates there
are no more capability structures in this function.
Sticky
Bit Reset
Value
Bit Access
0h
RO
26.2.1.22 Offset 5Ah: DP_BASE - Debug Port Base Offset Register
This register is hardwired to 20A0h, which indicates that the Debug Port Registers
begin at offset A0h in the USB 2.0 function’s memory space.
Table 26-24. Offset 5Ah: DP_BASE - Debug Port Base Offset Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 5Ah
Offset End: 5Bh
Size: 16 bit
Default: 20A0h
Power Well: Core
Bit Range
15 :13
12 :00
Bit Acronym
Bit Description
Sticky
BNBR
DPO
BAR Number: This field is hardwired to 001b to indicate
the memory BAR at offset 10h in the EHCI configuration
space.
Debug Port Offset: This field is hardwired to 0A0h to
indicate that the debug port registers begin at offset A0h
in the EHCI memory range.
Bit Reset
Value
001h
0A0h
Bit Access
RO
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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