EP80579 Datasheet, PDF (1101/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
28.1.1.5 Offset CF9h: RST_CNT - Reset Control Register
Table 28-7. Offset CF9h: RST_CNT - Reset Control Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: CF9h
Offset End: CF9h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
FULL_RST
RST_CPU
SYS_RST
Reserved
Reserved
Full Reset: This bit is used to determine the states of
SLP_S3#SLP_S4# and SLP_S5# after a hard reset (not
soft reset).
0 = SLP_S3#, SLP_S4# and SLP_S5# are kept high.
1 = Full reset, driving SLP_S3#, SLP_S4# and SLP_S5#
low for 3–5 seconds if the following conditions are
met:
• SYS_RST = 1 (bit 1 of this register) (Hard Reset not
soft reset).
• RST_CPU is written from 0 to 1(bit 2 of this register).
• After PWROK going low (with RSMRST# high), or after
two TCO timeouts.
When this bit is set, it also causes the full power cycle
(SLP_S3/4/5# assertion) in response to SYSRESET#,
PWROK#, and Watchdog timer reset sources.
Reset CPU: This bit causes either a hard or soft reset to
the IA-32 core depending on the state of the SYS_RST bit
(bit 1 in this same register).
Software causes the reset by setting this bit from a 0 to a
1.
System Reset: This bit determines the type of reset
caused via RST_CPU (bit 2 of this register).
0 = And RST_CPU goes from 0 to 1 (Soft Reset), then it
forces INIT# active for 16 PCI clocks.
1 = And RST_CPU goes from 0 to 1 (Hard Reset), then it
forces PLTRST# (and PCIRST#) and SUS_STAT#
active for 5 to 6 ms. The IICH main power well is
reset when this bit is 1 (and some suspend well logic
may also be reset).
Reserved
Bit Reset
Value
00h
0b
0b
0b
0b
Bit Access
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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