EP80579 Datasheet, PDF (738/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.1.7 Offset 0Eh: HTYPE: Header Type Register
Table 19-8. Offset 0Eh: HTYPE: Header Type Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 0Eh
Offset End: 0Eh
Size: 8 bit
Default: 80H
Power Well: Core
Bit Range
07
06 :00
Bit Acronym
Bit Description
MFD
HTYPE
Multi-function Device: This bit is hardwired to ‘1’ to
indicate a multi-function device.
Header Type: Identifies the header layout of the
configuration space, which is a generic device.
Sticky
Bit Reset
Value
Bit Access
1
RO
00h
RO
19.2.1.8
Offset 2Ch: SID: Subsystem Identifiers Register
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# deassertion.
Table 19-9. Offset 2Ch: SID: Subsystem Identifiers Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 2Ch
Offset End: 2Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 :16
15 :00
Bit Acronym
Bit Description
SSID
SSVID
Subsystem ID: This is written by BIOS. No hardware
action taken on this value.
Subsystem Vendor ID: This is written by BIOS. No
hardware action taken on this value.
Sticky
Bit Reset
Value
Bit Access
0000h
RWO
0000h
RWO
19.2.2
19.2.2.1
ACPI/GPIO Configuration Registers
Offset 40h: ABASE: ACPI Base Address Register
ABASE sets the base address in I/O space for the ACPI and TCO I/O registers (see
Section 27.3.3, “General Power Management I/O-Mapped Registers” on page 1055).
These registers can be mapped anywhere in the 64 K I/O space on 128-byte
boundaries.
Intel^® EP80579 Integrated Processor Product Line Datasheet
738
August 2009
Order Number: 320066-003US