EP80579 Datasheet, PDF (490/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.42 Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register
This register enables the memory controller to generate an MCERR# signal on the FSB
for various error flags. When an error flag is set in either the DRAM_FERR or
DRAM_NERR registers (see Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First
Error Register” and Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error
Register”), hardware generates an MCERR# signal on the FSB when enabled in the
DRAM_MCERRCMD register.
Note that software should enable one and only one message type for a given error flag.
Table 16-96. Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 8Eh
Offset End: 8Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Memory Test Complete MCERR# Enable: Generate
MCERR# when Bit 7 of DRAM_FERR or DRAM_NERR is set.
MTC_MCERR _{0 = Disable}
N
1 = Enable
Poisoned Write to DRAM MCERR# Enable: Generate
MCERR# when Bit 6 of DRAM_FERR or DRAM_NERR is set.
PWD_MCERR _{0 = Disable}
N
1 = Enable
Reserved Reserved
N
Error Threshold Detect MCERR# Enable: Generate
MCERR# when Bit 3 of DRAM_FERR or DRAM_NERR is set.
ETD_MCERR _{0 = Disable}
N
1 = Enable
Scrubber Data Error MCERR# Enable: Generate
MCERR# when Bit 2 of DRAM_FERR or DRAM_NERR is set.
SDE_MCERR _{0 = Disable}
N
1 = Enable
Uncorrectable Read Memory ErrorMCERR# Enable:
Generate MCERR# when Bit 1 of DRAM_FERR or
URM_MCERR ^{DRAM_NERR is set.}
N
0 = Disable
1 = Enable
Correctable Read Memory Error MCERR# Enable:
Generate MCERR# when Bit 0 of DRAM_FERR or
CRM_MCERR ^{DRAM_NERR is set.}
N
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
00b
0b
0b
0b
0b
Bit Access
RW
RW
RO
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
490
August 2009
Order Number: 320066-003US