EP80579 Datasheet, PDF (677/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.48 Offset ECh: DCR3 - Channel 3 Descriptor Control Register
Table 16-344.Offset ECh: DCR3 - Channel 3 Descriptor Control Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: ECh
Offset End: EFh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
The bit descriptions for this register are identical to those for DCR0 described in Section 16.6.1.12.
Bit Access
16.6.1.49 Offset 100h: DCGC - EDMA Controller Global Command
This register controls enabling and designation of priority channel.
Table 16-345.Offset 100h: DCGC - EDMA Controller Global Command
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 100h
Offset End: 103h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 03
02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
PCENBL
PCSLT
Reserved
Priority Channel Enable:
0 = No priority channel. The Priority Channel Select bits
are ignored.
1 = Enable the Priority Channel as programmed by the
Priority Channel Select.
Priority Channel Selects: When Priority Channel
Enable is set, the DMA channel selected by this field has
a higher priority than the others.
00 Channel 0 is the Priority Channel
01 Channel 1 is the Priority Channel
10 Channel 2 is the Priority Channel
11 Channel 3 is the Priority Channel
Bit Reset
Value
0
0b
00b
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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