EP80579 Datasheet, PDF (707/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-27. Offset 3410h: GCS - General Control and Status Register (Sheet 2 of 3)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3410h
Offset End: 3413h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Boot BIOS Straps: This field determines the destination
of accesses to the BIOS memory range.
Bit Reset
Value
Bit Access
11 : 10
09
08 : 07
06
05
04
03
BBS
SERM
Reserved
FME
NR
AME
Reserved
00 = SPI
01 = Reserved
10 = Reserved.
11 = LPC
• When SPI or LPC is selected, the range that is
decoded is further qualified by other configuration bits
described in the respective sections. The value in this
field can be overwritten by software as long as the
BIOS Interface Lock-Down (bit 0) is not set.
Server Error Reporting Mode:
0 =The IICH is the final target of all errors. The IMCH
sends a DO_SERR messages to the IICH for the purpose
of generating NMI.
1 = The IMCH is the final target of all errors from PCI
Express and NSI. In this mode, if the IICH detects a fatal,
non-fatal, or correctable error on NSI, it sends one of
ERR_FATAL, ERR_NONFATAL, or ERR_CORR to IMCH.
Reserved
FERR# MUX Enable: This bit enables FERR# to be a CPU
break event indication.
0 = does not examine FERR# during a C2, or C4 state as a
break event.
1 = IICH examines FERR# during a C2, or C4 state as a
break event.
No Reboot: This bit is set when the “No Reboot” strap is
sampled high on PWROK. This bit may be set or cleared by
software if the strap is sampled low but may not override
the strap when it indicates “No Reboot”.
0 = The TCO timer does not count down and generate the
SMI# on the first timeout, but reboots on the second
timeout.
1 = The TCO timer counts down and generates the SMI#
on the first timeout, but does not reboot on the second
timeout.
Alternate Access Mode Enable:
0 = Read-only registers cannot be written, and write-only
registers cannot be read. See Section 27.6 for details.
1 = Read-only registers can be written, and write-only
registers can be read. See Section 27.6 for details.
Reserved
Strap
RW
Special
0h
RW
0h
0h
RW
Strap
RW
0h
RW
0b
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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