EP80579 Datasheet, PDF (326/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 12-12.Source in Decrement and Destination in 4-Byte Granularity Constant Mode
Transfer
64-bit Source
MSB
Memory
LSB
ADDRESS
7
6
5
4
3
2
1
A000 0200H
15 14 13 12
11 10
9
8 _{A000 0208H}
20 19 18 17 16
A000 0210H
Data Block Transfer
64-bit Destination
17 18 19 20
13 14 15 16
1
2
3
4
4001 0300H
4001 0300H
4001 0300H
4001 0300H
Programmed Values
EDMACTL 0000 0088H
SUAR/SAR A000 0214H
DUAR/DAR 4001 0304H
TCR
DCR
0000 0014H
0004 503FH
10
byte number _{Bus operation}
SOURCE
QWORD load@ A0000210
QWORD load@ A0000208
QWORD load@ A0000200
DESTINATION
DWORD store@ 40010304
(5 times)
12.5.2.4 Buffer and Memory Initialization Modes
The EDMA can be used to write a constant value to local memory or to memory
mapped I/O. As with normal transfers, descriptors are used to specify the memory
blocks to which the data contained in the Source Address Register is written.
When buffer or memory initialization modes are selected, the data in the SAR is sent to
the destination address. No data is fetched. Data is transferred in 32-bit replicated
chunks to the destination. The transfers will continue until the byte count register is
satisfied.
12.5.2.4.1
Memory Initialization Mode
Memory initialization mode transfers can be to memory or to memory mapped I/O. In
this mode, the destination can be specified down to the byte address.
Figure 12-13 illustrates memory initialization to an arbitrary destination address.
Intel^® EP80579 Integrated Processor Product Line Datasheet
326
August 2009
Order Number: 320066-003US