EP80579 Datasheet, PDF (1663/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.23 Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per
Ethernet Channel)
Register
Name
TS_SrcUUID0Lo
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SourceUUID0_Low[31:0]
*Address offsets per channel…
Channel 0 = 0x058
Channel 1 = 0x078
Channel 2 = 0x098
Channel 3 = 0x0B8
Channel 4 = 0x0D8
Channel 5 = 0x0F8
Channel 6 = 0x118
Channel 7 = 0x138
Table 41-33. Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per Ethernet
Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
0058h at
Offset Start: 20h
Offset End: 005Bh at
20h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 0
When a Delay_Req message in Master mode, or a Sync
message in Slave mode, is received with no errors, the
SourceUUID0_L
ow
Source UUID of the message is captured. The source UUID
is located in bytes 64 through 69 of the Ethernet message,
and this register contains the lower 32 bits of the source
UUID. This register is read-only. At reset, the value in the
register is 0, which is not a valid Source UUID value.
Bit Reset
Value
0000h
Bit Access
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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