EP80579 Datasheet, PDF (16/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16.5.1.14
16.5.1.15
16.5.1.16
16.5.1.17
16.5.1.18
16.5.1.19
16.5.1.20
16.5.1.21
16.5.1.22
16.5.1.23
16.5.1.24
16.5.1.25
16.5.1.26
16.5.1.27
16.5.1.28
16.5.1.29
16.5.1.30
16.5.1.31
16.5.1.32
16.5.1.33
16.5.1.34
16.5.1.35
16.5.1.36
16.5.1.37
16.5.1.38
16.5.1.39
16.5.1.40
16.5.1.41
16.5.1.42
16.5.1.43
16.5.1.44
16.5.1.45
16.5.1.46
16.5.1.47
16.5.1.48
16.5.1.49
16.5.1.50
16.5.1.51
16.5.1.52
16.5.1.53
16.5.1.54
16.5.1.55
16.5.1.56
16.5.1.57
16.5.1.58
16.5.1.59
16.5.1.60
16.5.1.61
16.5.1.62
16.5.1.63
16.5.1.64
16.5.1.65
DQS Calibration Registers................................................................. 616
Offset B4h: DQSOFCS00 - DQS Calibration Register ............................. 617
Offset B8h: DQSOFCS01 - DQS Calibration Register ............................. 617
Offset C6h: DQSOFCS02 - DQS Calibration Register ............................. 618
Offset BCh: DQSOFCS10 - DQS Calibration Register............................. 618
Offset C0h: DQSOFCS11 - DQS Calibration Register ............................. 619
Offset C7h: DQSOFCS12 - DQS Calibration Register ............................. 619
WPTRTC DDR I/O Write Pointer Timing............................................... 620
Offset CCh: WPTRTC0 - Write Pointer Timing Control 0 Register ........... 620
Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register ............ 621
DDQSCVDP and DDQSCADP.............................................................. 621
Offset D4h: DDQSCVDP0 - DQS DELAY CALIBRATION VICTIM PATTERN 0
Register ......................................................................................... 621
Offset D8h: DDQSCVDP1 - DQS DELAY CALIBRATION VICTIM PATTERN 1
Register ......................................................................................... 622
Offset DCh: DDQSCADP0 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
0 Register ...................................................................................... 622
Offset E0h: DDQSCADP1 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
1 Register ...................................................................................... 622
Offset F0h: DIOMON - DDR I/O Monitor Register ................................. 623
Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register
624
Offset C8h: DRAMDLLC - DDR I/O DLL Control Register ........................ 625
Offset E8h: FIVESREG - Fixed 5s Pattern Register................................ 625
Offset ECh: AAAAREG - Fixed As Pattern Register ............................... 626
Memory BIST Registers .................................................................... 626
Offset 140h: MBCSR - MemBIST Control Register ............................... 626
Offset 144h: MBADDR - Memory Test Address Register ........................ 629
Offset 148h: MBDATA[0:9] - Memory Test Data Register ...................... 629
Offset 19Ch: MB_START_ADDR - Memory Test Start Address
Register ......................................................................................... 631
Offset 1A0h: MB_END_ADDR - Memory Test End Address Register......... 632
Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed
Register ......................................................................................... 633
Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register .
633
Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0 ................. 634
Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0 ................. 634
Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0 ................. 634
Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0 ................. 635
Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0 ................. 635
Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1 ................. 635
Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1 ................. 636
Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1 ................. 636
Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1 ................. 636
Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1 ................. 637
Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2 ................. 637
Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2 ................. 637
Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2 ................. 638
Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2 ................. 638
Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2 ................. 638
Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3 ................. 639
Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3 .................. 639
Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3 .................. 639
Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3 .................. 640
Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3 ................. 640
Offset 260h: DDRIOMC0 - DDR IO Mode Control Register 0................... 640
Offset 264h: DDRIOMC1 - DDR IO Mode Control Register 1................... 641
Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2................... 644
Offset 284h: WL_CNTL[4:0] - Write Levelization[4:0] Control
Intel^® EP80579 Integrated Processor Product Line Datasheet
16
August 2009
Order Number: 320066-003US