EP80579 Datasheet, PDF (654/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-297.Offset 00h: CCR0 - Channel 0 Channel Control Register (Sheet 2 of 3)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Channel Resume:
0 = Cleared when:
• The channel completes a DMA transfer and the Next
Descriptor Address Register is not zero. In this
case, the channel proceeds to the next descriptor in
the chain (resumes).
• The channel is idle or the channel completes a DMA
transfer and the Next Descriptor Address Register is
zero.
Bit Reset
Value
Bit Access
1 = Causes the channel to resume chaining by re-
reading the current descriptor located in local
03
CRSM
system memory and reloading the Next Descriptor
Address Register when the channel is idle (the
Channel Active bit in the CSR is clear) or when the
channel completes execution of the current
descriptor.
Once set, software cannot clear this bit. The IMCH
prevents this bit from being set when either the stopped
or aborted bit is set in the CSR. Software must clear the
CSR stopped and aborted bits before attempting to
resume the current descriptor chain. If the CSR end of
chain bit was set, the DMA channel clears the end of
chain bit when the current descriptor chain resumes.
Refer to Chapter 12.0, “Enhanced Direct Memory Access
Controller (EDMA)” for details on the suspend and
resume function.
Stop:
0 = Cleared only by the IMCH, once the Channel Active
bit is cleared and the DMA Stopped bit is set.
1 = Causes the current DMA transfer to stop. The
channel does not request the bus on the source
side. Any data in the queue is emptied to the
02
STPDMA
destination side, and all relevant bits in the CCR
(bits 03:00) and CSR (Channel Active bit) are
cleared. This bit has priority over the Suspend DMA
bit. Once set, this bit cannot be cleared by the
software. Software must be very careful in setting
this bit since any DMA transfer, once stopped,
cannot be restarted from that point.
Suspend: This has no effect on the Channel Active bit.
0 = Software clears this bit once the DMA Suspended
bit is set. Clearing this bit restarts the DMA transfer
from the point it was suspended, and clears the
DMA Suspended bit in the CSR. Refer to
Chapter 12.0, “Enhanced Direct Memory Access
Controller (EDMA)” of for details on the DMA
01
SUSDMA
suspend function.
1 = Allows the current descriptor to finish, but
suspends channel chaining. The channel continues
to request the bus on the source side for the
current descriptor. When the data in the queue for
this descriptor is emptied to the destination side,
the channel sets the DMA Suspended bit in the
CSR.
0b
RWS
0b
RWS
0b
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
654
August 2009
Order Number: 320066-003US