EP80579 Datasheet, PDF (1067/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-18. Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register
(Sheet 1 of 2)
Description:
View: PCI
Size: 32 bit
BAR: PMBASE (IO)
Default: 00000000h
Bus:Device:Function: 0:31:0
Offset Start: 2Ch
Offset End: 2Ch
Power Well: Resume^a
Bit Range
31 : 16
15
14
13
12
11
10
09
08
07
06
05
Bit Acronym
Bit Description
Sticky
GPIn_EN
These bits enable the corresponding GPI[n]_STS bits
being set to cause an SCI and/or wake event. These bits
are cleared by RSMRST#.
Note: Mapping is as follows: bit 31 corresponds to
GPI[15]... and bit 16 corresponds to GPI:[0].
Reserved Reserved
Reserved Reserved
PME_B0_EN
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to
generate a wake event and/or an SCI or SMI#.
PME_B0_STS can be a wake event from the S1/S3/
S4 state, or from S5 (if entered via SLP_TYP and
SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
Note: It is only cleared by Software or RTEST#. It is
not cleared by CF9h writes. This bit is in the
RTC well.
Reserved Reserved
PME_EN
0 = Disable.
1 = Enables the setting of the PME_STS to generate a
wake event and/or an SCI. PME# can be a wake
event from the S1/S3/S4 state or from S5 (if
entered via SLP_EN, but not power button
override).
This bit is only cleared by software or RTEST#. It is not
cleared by CF9h writes. This bit is in the RTC well.
Reserved Reserved
PCI_EXP_EN
0 = Disable SCI generation upon PCI_EXP_STS bit
being set.
1 = Enables an SCI when PCI_EXP_STS bit is set.
This is used to allow the PCI Express ports, including the
link to the IMCH, to cause an SCI due to wake/PME
events.
RI_EN
When RI_EN and RI_STS are both set, a Wake event will
occur. If RI_EN is not set, then when RI_STS is set, no
Wake event will occur.
0 = Disable.
1 = Enables the setting of the RI_STS to generate a
wake event.
This bit is only cleared by software or RTEST#. This bit
is in the RTC well.
Reserved Reserved
TCOSCI_EN
When TCOSCI_EN and TCOSCI_STS are both set, an
SCI will be generated.
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate
an SCI.
This bit is in the resume well. This bit is only cleared by
software or RSMRST#. It is not cleared by CF9h writes.
Reserved Reserved
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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