EP80579 Datasheet, PDF (708/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-27. Offset 3410h: GCS - General Control and Status Register (Sheet 3 of 3)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3410h
Offset End: 3413h
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
02
01
Bit Acronym
Bit Description
Sticky
RPR
Reserved
Reserved Page Route: Determines where to send the
reserved page registers. These addresses are sent to PCI
or LPC for the purpose of generating POST codes. The I/O
addresses modified by this field are: 80h, 84h, 85h, 86h,
88h, 8Ch, 8Dh, and 8Eh.
0 = Writes are forwarded to LPC, shadowed within the
IICH, and reads are returned from the internal shadow.
1 = Writes are forwarded to PCI, shadowed within the
IICH, and reads are returned from the internal shadow.
Note: If some writes are done to LPC/PCI to these I/O
ranges, and then this bit is flipped, such that
writes now go to the other interface, the reads do
not return what was last written. Shadowing is
performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h,
98h, 9Ch, 9Dh, and 9Eh, are always decoded to LPC.
Reserved
Bit Reset
Value
0h
0h
Bit Access
RW
Top Swap Lock-Down:
00
TSLD
0 = This bit can only be written from 0 to 1 once. BUC.TS
can be changed.
1 = Prevents BUC.TS from being changed.
0h
RWO
17.1.6.4
Offset 3414h: BUC - Backed Up Control Register
All bits in this register are in the RTC well and only cleared by RTEST.
Table 17-28. Offset 3414h: BUC - Backed Up Control Register (Sheet 1 of 2)
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3414h
Offset End: 3417h
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 : 03
Bit Acronym
Reserved Reserved
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
Intel^® EP80579 Integrated Processor Product Line Datasheet
708
August 2009
Order Number: 320066-003US