EP80579 Datasheet, PDF (1243/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.5 Offset 04h: PCICMD – Device Command Register
Table 35-10. Offset 04h: PCICMD: Device Command Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: 04h
Offset End: 05h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: 04h
Offset End: 05h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: 04h
Offset End: 05h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 : 11
10
09
08
07
06
05
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
INTD
FBTB
SER
Reserved
PER
VPS
MWE
SS
BM
MEM
IO
Reserved
Interrupt Disable
Fast Back-to-Back Enable
SERR# Enable
Reserved
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate
Special Cycle
Bus Master Capable
Memory Space Enable: Setting this bit enables access to
the memory regions the device claims through its BARs.
I/O Space Enable: Setting this bit enables access to the
I/O regions the device claims through its BARs.
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RO
RO
RV
RO
RO
RO
RO
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1243